1. Field of the Invention
The present invention relates to a leadframe structure used for making electrical connections to a semiconductor device. More particularly, the present invention relates to a multilevel leadframe configuration for improving reliability and performance by reducing the number of wires that must extend over or "jump" a bus bar in a lead-over-frame configuration.
2. State of the Art
A typical semiconductor chip is generally constructed from a semiconductor die which is in electrical communication with a component known as a leadframe. The semiconductor die and leadframe are usually sealed in an encapsulant, such as a transfer-molded plastic (filled polymer), wherein portions of the leadframe extend from the encapsulant to ultimately, after fitting and trimming, form electrical communication between the semiconductor die and external circuitry, such as a printed circuit board ("PCB") or the like.
The leadframe is typically formed from a single continuous sheet of metal by a metal stamping or etching operation. As shown in FIG. 15, a conventional lead frame 200 generally consists of an outer supporting frame 202, a central semiconductor chip or "die attach" supporting pad 204 and a plurality of lead fingers 206, each lead finger 206 extending toward the central chip supporting pad 204. Ultimately, the outer supporting frame 202 of the leadframe 200 is removed after wire bonds are connected between contact pads of a semiconductor die (not shown) and the lead fingers 206.
As shown in FIG. 16 (components common to FIGS. 15 retain the same numeric designation), a semiconductor die 208 having a plurality of bond pards 210 is secured to the central semiconductor chip supporting pad 204 (such as by solder or epoxy die-attach material, or a double-sided adhesive film). The leadframe 200, with the semiconductor die 208 attached thereon, is placed into a wire bonding apparatus including a clamp assembly for holding the leadframe and die assembly, as well as clamping the lead fingers 206 for bonding (not shown). Bond wires 212 of gold, aluminum, or other metals and alloys known in the art are attached, one at a time, from each bond pad 210 on the semiconductor die 208 and to its corresponding lead finger 206. The bond wires 212 are generally attached through one of three industry-standard wire bonding techniques, depending on the wire material employed: ultrasonic bonding--using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding--using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding--using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. After wirebonding, the assembly can be encapsulated as discussed above.
U.S. Pat. No. 4,862,245 issued Aug. 29, 1989 to Pashby et al. ("the Pashby patent") illustrates a so-called "leads over chip" arrangement ("LOC") on the semiconductor die. As shown in FIG. 17, in an LOC arrangement 300, a plurality of lead fingers 302 extends over the active surface of a semiconductor die 304 toward a line of bond pads 306 wherein bond wires 308 make the electrical connection between the lead fingers 302 and the bond pads 306. An alpha barrier 310, such as a polyimide (for example, Kapton.TM.) film, is adhered between the semiconductor die 304 and the lead fingers 302. The LOC configuration as exemplified by the Pashby patent eliminates the use of the previously-referenced central die attach pad, may assist in limiting the ingress of corrosive environment contaminants, achieves a larger portion of the lead finger path length encapsulated in the packaging material, reduces electrical resistance caused by the bond wires (i.e., the longer the bond wire, the higher the resistance), and reduces the potential for wire sweep problems aggravated by long wire loops.
In a conventional configuration (non-LOC), some of the lead fingers carry input or output signals to or from the semiconductor die while others provide a power source or a ground. In an LOC configuration, the lead fingers likewise provide the input or output signals to or from the semiconductor device, but the power source and ground are typically provided by bus bars. The bus bars form an elongated contact in close proximity to the bond pads and typically lie in a perpendicular orientation to the other lead fingers. It is, of course, understood that the bus bars can also carry an input or an output signal which is usually common to more than one bond pad.
A conventional LOC configuration 400, including bus bars, is shown in FIG. 18. A semiconductor die 402 is housed within the integrated circuit chip package 400. A leadframe 404 includes a plurality of lead fingers 406 and 408 extending over the surface of the die toward bond pads 410. The leadframe 404 also includes bus bars 412 and 414. The bus bars 412 and 414 and the lead fingers 406 and 408 are connected to the bond pads 410 by bond wires 416. One problem with the conventional LOC configuration is that the bond wires 416 must jump or cross over the bus bars 412 and 414 in order to make their respective connections with the bond pads 410. This jumping gives rise to the possibility of shorting between the lead fingers 406 and 408 and the bus bars 412 and 414. In addition, the bond wires 416 must be of extended length to jump the bus bars 412 and 414. This additional bond wire length also adds undesirable inductance and capacitance to the signals, potentially degrading the electrical performance of the semiconductor device. Moreover, the height of the bond wires 416 jumping over the bus bars 412 and 414 are also problematic for thin profile semiconductor packages, such as TSOPs (thin, small outline packages). The bond wires 416 may actually extend out of the encapsulant material used to protect such thin profile semiconductor packages.
U.S. Pat. No. 4,796,078 issued Jan. 3, 1989 to Phelps, Jr. et al. illustrates a multi-layered leadframe assembly. A semiconductor die is bonded to a recess in a first, lower leadframe. Wire bonds extend from lead fingers of the first leadframe terminating short of the sides of the die to peripheral bond pads. A second, upper leadframe of an LOC configuration is secured to the top of the semiconductor die and the first leadframe with an adhesive tape. The lead fingers of the second leadframe extending over the die have selected wire bonds made to central terminals by bondwires. Thus, it appears that LOC technology is integrated with a conventional peripheral-lead attachment. One problem with this type of configuration is that it requires a central die attach pad that was essentially eliminated by use of LOC technology.
U.S. Pat. No. 5,461,255 issued Oct. 24, 1995 to Chan et al. also illustrates a multi-layered leadframe assembly. As shown in FIG. 19, the Chan type of main leadframe 500 comprising a plurality of leads 502 is adhered to the active face 504 of an integrated circuit chip 506 by an insulating adhesive tape strip 508. A bus leadframe 510 comprising a plurality of conductive leads 512 is then adhered to the opposite, upper side of the main leadframe 500 by an insulating adhesive tape strip 514. The selected lead 502 of the main leadframe 500 are welded at spot welds 516 to the selective leads 512 of the bus leadframe 510. The selective leads 502 of the main leadframe 500 are electrically connected at their inner ends to bond pads 518 on the integrated circuit chip 504 by tab bonds 520. Alternatively, wire bonds may be used. This configuration suffers from at least one disadvantage in that the bus leadframe 510 comprises a plurality of conductive leads 512 which are connected at their ends to select leads 502 of the main leadframe 500 at spot welds 516. Thus, a plurality of leads of the main lead frame is required to electrically connect the bus bar to the bond pads. As semiconductor circuits have become smaller and more complex, it has become more important to limit the number of leads used for power and ground sources because the leads are required for carrying signals and because of physical limitations on reducing the size of the leads. Therefore, it is important to conserve as many leads as possible for signal transmission by reducing the number used for power and ground source. In addition, the plurality of spot welds increases the time and number of operations required to manufacture the integrated circuit package, thus increasing the cost of production.
U.S. Pat. No. 5,331,200 issued Jul. 19, 1994 to Teo et al. illustrates a multi-layered leadframe assembly to facilitate direct inner lead bonding for both the power bus and the main leadframe. As shown in FIG. 20, bus bar frames 600 and 602 are separate bars that are attached to both main leadframe fingers 604 and 612. Bus bar frames 600 and 602 provide bus bar bond fingers 606 and 608 that extend to bond pads 610 for connection directly to the bond pads using inner lead bonding techniques. The bus bar frames 600 and 602 are joined to the main leadframe by external lead bonding methods or adhesive tape. One disadvantage of this configuration is the use of inner lead bonding techniques, which may require tooling changes and design changes for a system previously constructed to use wire bonding techniques. Another disadvantage of the inner lead bonding technique is the need to redesign the location of the bond fingers when the design of the integrated circuit is changed. Thus, should the location of bond pads be changed due to a change (such as a die "shrink") in the integrated circuit design, new bus bar frames will be required with the bus bar bond fingers reconfigured.
U.S. Pat. No. 5,286,999 issued Feb. 15, 1994 to Chiu illustrates a conventional LOC leadframe with the bus bar folded under the lead fingers. As shown in FIGS. 21-22, a bus bar 700 is folded under lead fingers 702 and connected to the lead fingers 702 at the outer ends of a row of lead fingers 702. A strip of insulating material 704 is placed between the bus bar 700 and the lead fingers 702. The lead fingers 702 and the bus bar 700 are attached to bond pads 706 on the semiconductor chip 708 by bond wires 710. The bus bar 700 and lead fingers 702 are etched so that the thickness of the lead finger, bus bar, and tape when folded together is no more than the thickness of the leadframe lying outwardly of the folded assembly. One problem with this type of configuration is the difficulty in folding the bus bar under the lead fingers. There is also a chance of damaging the leadframe assembly while attempting to fold the bus bar under the lead fingers.
U.S. Pat. No. 5,550,401 issued Aug. 27, 1996 to Maeda illustrates a conventional LOC leadframe with the bus bar folded back over the lead finger. As shown in FIGS. 23-24, a leadframe 800 is formed by folding a bus bar 802 back over lead fingers 804. The bus bar 802 also includes finger portions 806 which are formed in folding back the bus bar 802. These finger portions 806 align in the same plane with the lead fingers 804 and are attached coextensive with the lead fingers 804. While this type of configuration eliminates the problem associated with lead wires crossing over the bus bar 802 or other lead fingers 804, the process requires precise folding of the bus bar 802 back over the lead fingers 804 without bending the finger portions 806 from their planar alignment with the lead fingers 804. This precise processing step would increase the processing cost of the leadframe.
Thus, it would be advantageous to develop a simple and relatively inexpensive leadframe configuration such that the bond pads could be electrically connected to the lead fingers and the bus bars using typical wire bonding techniques without having lead wires cross over or "jump" the bus bars or other lead fingers.